IEEE Trans Ultrason Ferroelectr Freq Control 2006 Feb;53(2):274-83
Department of Electrical and Computer Engineering, Auburn University, Auburn, AL 36849-5201, USA.
This paper presents a novel direct digital frequency synthesis (DDFS) ROM compression technique based on two properties of a sine function: (a) piecewise linear technique to approximate a sinusoid, and (b) variation in the slope of the sinusoid at different phase angles. In the proposed DDFS architecture the ROM stores a few of the sinusoidal values, and the interpolation points between the successive stored values are calculated using linear and nonlinear addressing schemes. The nonlinear addressing scheme is used to adaptively vary the number of interpolation points as the slope of the sinusoid changes, leading to a greatly reduced ROM size. The proposed architecture achieves a high compression ratio with a spurious response comparable to that of recent ROM compression techniques. To validate the proposed DDS architecture, the linear, nonlinear, and conventional DDS ROM architectures were implemented in a Xilinx Spartan II FPGA and their spurious performances were compared.